1. Field of the Invention
The present invention relates to a delay circuit, for example, a delay circuit having a stable delay time or a voltage-controlled delay circuit capable of controlling a delay time in accordance with a control voltage, furthermore, a voltage-controlled oscillation circuit capable of controlling an oscillation frequency in accordance with a control voltage, a delay adjustment circuit using a delay circuit, a DLL (Delay Locked Loop) circuit, and a PLL (Phase Locked loop) circuit.
2. Description of the Related Art
A delay time of a delay circuit or a voltage-controlled delay circuit changes when there is a power source noise, such as changes of a power source voltage. Further, in an oscillation circuit configured by a plurality of delay circuits connected in a ring, it is possible to configure a voltage-controlled oscillation circuit (VCO) by controlling the delay times of the delay circuits in accordance with control voltages. When power source noise arises, the delay times of the delay circuits change, so the oscillation frequency of the VCO also changes accordingly.
In a PLL circuit configured by a phase comparison circuit, loop filter, VCO, etc., changes of the oscillation frequency of the VCO can be reduced by feedback control. Namely, when the oscillation frequency of the VCO changes due to power source noise, the deviations of phase and frequency of the oscillation signal generated by the effect of the power source noise can be corrected to a certain extent by detecting the deviations of the phase and frequency of the oscillation signal by the phase comparison circuit, generating a control signal in accordance with the result of detection of the phase deviation, and correcting the oscillation frequency of the VCO and therefore it is possible to suppress generation of jitter by the power source noise.
In displaying a video signal of a personal computer (PC) and displaying OSD (On Screen Display) letters of a television monitor, a dot clock signal multiplied by a PLL circuit using a horizontal synchronizing signal Hsync as a reference clock is generated. Graphic data and text data are displayed by this dot clock signal. When jitter of the PLL circuit is not very small, it is visually perceived as a flicker or waving on the screen. For example, if exactly 24 dots/letterxc3x9732 letters=768 dots are displayed in the horizontal direction, the effective horizontal period is 70%, and the allowable amount of jitter is xc2x1xe2x85x9 dot, the amount of jitter has to be suppressed to about xc2x11/(768÷0. 7xc3x978)=xc2x1{fraction (1/8777)} of the cycle of the horizontal synchronization signal. The standard of the amount of jitter is xc2x17.1 ns when the frequency of the horizontal synchronization signal fH=15.734 kHz, while the standard of the amount of jitter is xc2x12.4 ns when the frequency of the horizontal synchronization signal fH=46.250 kHz. Further, the standard of the amount of jitter becomes xc2x11.1 ns when the frequency of the horizontal synchronization signal fH=106.250 kHz.
It might appear that the target values of the amount of jitter described above can be easily satisfied, however, in the case of a PLL circuit of a high multiplication factor, when the cycle of the reference clock of the PLL circuit is Tref and the frequency thereof is fref, an effect due to digital noise generated in a much shorter period than Tref is corrected in its average value portion by a feedback loop of the PLL circuit, so the remaining portion deviated from the average value affects the amount of jitter.
As Tref becomes longer, the deviated portion is added, so when the amount of jitter is Tj, it is presumed that the relationship of
(Tjxcex1{square root over (Fref)}=1{square root over (fref)})
stands.
FIG. 45 shows the relationship of a target value of the amount of jitter and ability of a PLL. As shown in the figure, there arises a case where even if a target value is cleared at a frequency of the horizontal synchronization signal fH=15.734 kHz, target values cannot be cleared at frequencies of the horizontal synchronization signal fH=47.250 kHz and fH=106.250 kHz.
Namely, the amount of jitter at fref=100 kHz is presumed to become 14 times as much as the amount of jitter at fref=20 MHZ. The actual amount of jitter becomes still larger than this. Therefore, it is very difficult to design a PLL circuit of a very high multiplication factor wherein the multiplication factor is several thousand to ten thousand times.
There are many video signal standards for video signals of personal computers. For the horizontal synchronization signal, computers are required to be able to handle a frequency band of 31.436 kHz to 106.250 kHz.
Also, regarding TV monitors, a variety of specifications have come into existence along with the spread of digital broadcasting. For the horizontal synchronization signal, monitors are required to be able to handle a frequency band of 12.587 kHz to 47.250 kHz.
A PLL circuit used for such diverse applications is required to change characteristics of the filter etc. to match with the frequency fH of the horizontal synchronization signal. This cannot be done by changing outside parts, so it is preferable to design the PLL circuit to be built into the semiconductor integrated circuit except for some parts and to enable changes by a program.
A PLL circuit resistant to jitter even when receiving noise from other digital circuits is necessary when building it into a semiconductor integrated circuit.
PLL circuits have been designed by solving characteristic formulas of feedback loops, so the techniques for reducing jitter of a PLL or DLL have mainly focused on techniques for achieving both high speed pull-in and reduced jitter (making filter characteristics variable etc.)
It is considered better to reduce the gain of a PLL circuit by characteristic formulas to realize lower jitter, but when reducing the gain of the PLL circuit, there are problems that the pull-in speed declines and there is greater susceptibility to process variations. Various measures have therefore been taken in the circuit.
For example, an initial control voltage of the VCO is supplied by a digital/analog converter (DAC), and an output voltage of a charge pump when pull-in ends is stored. Rough control is performed by digitally changing the number of delay stages of the VCO circuit and a current supply ability of a current source transistor, while precise control is performed by an analog control voltage. Here, the circuit operates as a digital PLL in an unlocked state and operates as a PLL in a locked state. Measures are taken such as making the output current of the charge pump variable and making the output current of the charge pump small in a locked state etc.
Patent documents Japanese Unexamined Patent Publication (Kokai) No. 9-214340 xe2x80x9cPLL Circuitxe2x80x9d, Japanese Unexamined Patent Publication (Kokai) No. 9-172370 xe2x80x9cPLL Circuitxe2x80x9d, Japanese Unexamined Patent Publication (Kokai) No. 7-106959 xe2x80x9cPhase Synchronization Circuitxe2x80x9d, Japanese Unexamined Patent Publication (Kokai) No. 10-242851 xe2x80x9cPLL Circuitxe2x80x9d, etc. disclose PLL circuits improved as explained above.
However, since power source voltage dependency was not included in the characteristic formula of the feedback loop, designers of PLL circuits did not view design of a circuit having a small power source voltage dependency as being a general problem. Therefore, the above measures did not consider the jitter caused by power source noise in a locked statexe2x80x94which becomes a problem in a PLL of a high multiplication factor and low jitter used for displaying a video signal on a personal computer and displaying OSD letters on a TV monitor.
As prior art considering jitter caused by power source noise in a locked state, there is the patent document Japanese Unexamined Patent Publication (Kokai) No. 8-288801 xe2x80x9cLow Jitter Broad Frequency Range Voltage-Controlled Oscillatorxe2x80x9d. In the publication, there is reported that xe2x80x9can output frequency generated by a voltage-controlled oscillator is a linear function of a control voltage Vc. On the other hand, it changes together with a power source voltage Vdd according to an inverse square root function of a supply voltage . . . . A change of about 3% of the frequency generated by the voltage-controlled oscillator corresponds to a change of 10% of a high PSRR:Vddxe2x80x9d and that xe2x80x9cinverse relationship between a frequency and a supply voltage: this condition is useful in stabilizing a loopxe2x80x9d. The balance in the overall feedback loop was therefore considered, but high speed phenomena such as digital noise was not considered.
In recent years, in the field of ATM (Asynchronous Transfer Mode) communication etc., PLL by a voltage-controlled oscillator using a differential delay circuit and DLL by a voltage-controlled delay circuit (VCD circuit) using a differential circuit have been developed to deal with the increasingly higher frequency of system clocks and PLL or DLL being built into chips.
A differential circuit has a good CMRR (common mode rejection ratio). Furthermore, if designed well, it has a good PSRR (power supply rejection ratio) and becomes resistant to digital noisexe2x80x94which becomes a problem when building the circuit into the chip. In this way, differential circuit designers considered the design of a circuit having a small power source voltage dependency to be a general problem.
Since differential circuit does not require full swing of an input/output signal, it can operate at a high speed, but it has the disadvantage that the output amplitude is not constant and the delay time is liable to change since the signal does not fully swing. To solve this, a clamp circuit or feedback circuit for making the output amplitude of a VCO circuit and VCD circuit constant has been provided, and PLLs and DLLs having low jitter have been developed. Also, consideration has been given to the method of replacing a current source transistor connected to a current line side with a source-follower transistor to keep the effects of power source changes from being transferred to the differential transistor and controlling the oscillation frequency by a gate input voltage of the source follower.
A differential circuit is explained in detail in Masayuki MIZUNO et al., xe2x80x9cLow-Power and High-Speed LSI Technologies. A 0.18 xcexcm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCOxe2x80x9d, IEICE Trans. Electron (Inst. Electron. Inf. Commun. Eng.), Vol. E80-C, No. 12, pp. 1560 to 1571, 1997; the patent document Japanese Unexamined Patent Publication (Kokai) No. 9-214299 xe2x80x9cVoltage-Controlled Oscillatorxe2x80x9d and its related article Takehiko NAKAO et al., xe2x80x9cSingle-Chip 4-Channel 155 Mb/s CMOS LSI Chip for ATM SONET/SDE Framing and Clock/Data Recoveryxe2x80x9d, Dig. Tech. Pap., IEEE Int. Solid State Circuits Conf., Vol. 40, pp. 160 to 161, 448, 1997; etc.
In the above differential PLL circuit and DLL circuit, both of the D and /D transistors operate. Therefore, the power consumption and layout area become twice compared with a non-differential circuit. Since the input/output signal does not have to fully swing, the speed becomes high. For example, assuming that it is sufficient to swing about half the amplitude, the speed becomes about two times higher. However, since a clamp circuit and feedback circuit have to be attached, there are disadvantages that the power consumption is further increased and the speed does not become as high as expected. Also, since a signal which does not fully swing has to be converted to a signal which fully swings at the time of taking out an output signal, the duty is liable to go wrong. Further, the differential circuit has a large number of transistors connected in the vertical direction so measures have to be made to secure an operating margin when reducing the power source voltage of the semiconductor integrated circuit. Therefore, there are many technical problems in differential PLL circuits and DLL circuits.
An object of the present invention is to provide an inverter type delay circuit, a voltage-controlled oscillation circuit, a voltage-controlled delay circuit, a delay adjustment circuit, a DLL circuit, and a PLL circuit able to realize simplification of the circuit configuration, reduction of an effect of power source noise, and reduction of jitter by controlling a drive current supplied to an inverter delay element and using delay elements having different power source voltage dependencies.
To achieve the above object, a delay circuit of the present invention is a delay circuit having a delay stage having a drive current controlled in accordance with a bias voltage and having a delay time determined by the drive current, comprising an adding means for adding a change of a power source voltage to the bias voltage by a predetermined ratio and supplying a result of the addition to the delay stage.
Alternatively, in the present invention, preferably, the adding means includes an alternating current adding means for adding an alternating current component included in the amount of change of the power source voltage to the bias voltage.
Alternatively, in the present invention, preferably, the adding means comprises a direct current adding means for adding a direct current component included in the amount of change of the power source voltage to the bias voltage.
Alternatively, in the present invention, preferably, the delay stage comprises a MOS type inverter; a first current source transistor connected between the inverter and a supply line of the power source voltage and having a gate to which is applied a first bias voltage; and a second current source transistor connected between the inverter and a supply line of a reference voltage and having a gate to which is applied a second bias voltage.
Alternatively, in the present invention, preferably, the adding means comprises a first alternating current adding means for adding alternating current components included in an amount of change of the power source voltage to the first bias voltage and a second alternating current adding means for adding alternating current components included in the amount of change of the power source voltage to the second bias voltage.
Alternatively, in the present invention, preferably, the adding means comprises a first direct current adding means for adding direct current components included in the amount of change of the power source voltage to the first bias voltage and a second direct current adding means for adding direct current components included in the amount of change of the power source voltage to the second bias voltage.
Alternatively, in the present invention, preferably, the delay stage comprises a MOS type inverter; a plurality of first current source transistors each having one terminal connected to a supply line of the power source voltage and having a gate to which is applied a first bias voltage; a plurality of second current source transistors each having one terminal connected to a supply line of the power source voltage and having a gate to which is applied a second bias voltage; a first switching circuit connected between the first current source transistor and the inverter for selecting any one or more of output currents of the plurality of first current source transistors and supplying the same to the inverter; and a second switching circuit connected between the second current source transistor and the inverter for selecting any one or more of output currents of the plurality of second current source transistors and supplying the same to the inverter.
Alternatively, in the present invention, preferably, the delay stage comprises a MOS type inverter; a switching transistor each having one terminal connected to an output terminal of the inverter and a gate to which is applied the bias voltage; and a capacitor having one electrode connected to the other terminal of the switching transistor and having another electrode connected to a supply line of a reference voltage.
Alternatively, in the delay circuit of the present invention, preferably, the adding means comprises a capacitor connected between a supply line of the power source voltage and a supply line of the bias voltage and couples the alternating current components of a change of the power source voltage with the bias voltage.
Alternatively, according to the present invention, there is provided a delay circuit having a delay stage having a delay time determined by a supplied drive current, wherein the delay stage comprises a MOS type inverter; a first current source circuit for supplying a first drive current to the inverter in accordance with a first bias voltage; and a second current source circuit for supplying a second drive current having a power source voltage dependency different from that of the first drive current to the inverter.
Alternatively, in the present invention, preferably further provision is made of a first adding means for adding a change of the power source voltage to the first bias voltage by a first ratio and supplying a result of the addition to the first current source circuit and a second adding means for adding the change of the power source voltage to the second bias voltage by a second ratio and supplying a result of the addition to the second current source circuit.
Alternatively, according to the present invention, there is provided a delay circuit comprised of a plurality of delay stages having different power source voltage dependencies comprising first delay stages having a first power source voltage dependency and second delay stages having a second power source voltage dependency opposite to the first power source voltage dependency; the numbers of the first delay stages and the second delay stages being determined by a predetermined ratio.
Alternatively, in the present invention, preferably, the ratio of the first delay stages and the second delay stages is determined within a delay time when jitter of the delay circuit is not more than a desired target value.
Furthermore, in the present invention, preferably, further provision is made of third delay stages having suppressed power source voltage dependency of a delay time in addition to the first and second delay stages.
Alternatively, according to the present invention, there is provided a delay adjustment circuit for outputting a delay signal obtained by adding a predetermined time to an input signal, comprising a bias circuit for generating a bias voltage; a delay circuit for delaying the input signal by a plurality of different delay times controlled in accordance with the bias voltage and outputting a plurality of delay signals; and a selection circuit for selecting any one or more of the plurality of delay signals output from the delay circuit in accordance with a selection signal. Note that the above delay circuit has measures against power source noise as explained above and is suppressed in power source dependency of a delay time.
Alternatively, according to the present invention, there is provided a voltage-controlled delay circuit including a delay stage having a drive current controlled in accordance with a control voltage and having a delay time determined by the drive current, comprising an adding means for adding a change of a power source voltage to the control voltage by a predetermined ratio and supplying a result of the addition to the delay stage.
According to the present invention, there is provided a voltage-controlled delay circuit having a delay stage having a delay time determined by supplied drive currents, wherein the delay stage comprises a MOS type inverter; a first current source circuit for supplying a first drive current to the inverter in accordance with a first control voltage; and a second current source circuit for supplying a second drive current having a power source voltage dependency different from that of the first drive current to the inverter.
Alternatively, according to the present invention, there is provided a voltage-controlled delay circuit comprised of a plurality of delay stages having different power source voltage dependencies, comprising first delay stages having a delay time controlled in accordance with a control voltage and having a first power source voltage dependency and second delay stages having a delay time controlled in accordance with the control voltage and having a second power source voltage dependency opposite to the first power source voltage dependency; the numbers of the first delay stages and the second delay stages being determined by a predetermined ratio.
Alternatively, according to the present invention, there is provided a DLL circuit comprising a phase comparison means for comparing phases of an input signal and a delay signal and outputting a phase difference signal in accordance with a result of the comparison; a voltage output means for outputting a control voltage in accordance with the phase difference signal; and a voltage-controlled delay circuit for delaying the input signal by a delay time controlled in accordance with the control voltage and outputting the delay signal, wherein the voltage-controlled delay circuit has measures against power source voltage noise as explained above and is suppressed in power source voltage dependency of a delay time.
Alternatively according to the present invention, there is provided a voltage-controlled oscillation circuit comprising delay stages each having a drive current controlled in accordance with a control voltage and having a delay time determined by the drive current connected in a ring, comprising an adding means for adding a change of a power source voltage to the control signal by a predetermined ratio and supplying a result of the addition to the delay stages.
Alternatively, according to the present invention, there is provided a voltage-controlled oscillation circuit comprised of delay stages each having a delay time determined by a supplied drive current connected in a ring, wherein each delay stage comprises a MOS type inverter; a first current source circuit for supplying a first drive current to the inverter in accordance with a first control voltage; and a second current source circuit for supplying a second drive current having a power source voltage dependency different from that of the first drive current to the inverter.
Alternatively, according to the present invention, there is provided a voltage-controlled oscillation circuit comprised of a plurality of delay stages having different power source voltage dependencies connected in a ring, comprising first delay stages having a delay time controlled in accordance with a control voltage and having a first power source voltage dependency; and second delay stages having a delay time controlled in accordance with the control voltage and having a second power source voltage dependency opposite to the first power source voltage dependency; the numbers of the first delay stages and the second delay stages being determined by a predetermined ratio.
Alternatively, according to the present invention, there is provided a PLL circuit comprising a phase comparison means for comparing phases of a reference signal and an oscillation signal and outputting a phase difference signal in accordance with a result of the comparison; a voltage output means for outputting a control voltage in accordance with the phase difference signal; and a voltage-controlled oscillation circuit for oscillating at an oscillation frequency controlled in accordance with the control voltage and outputting an oscillation signal; wherein the voltage-controlled oscillation circuit has measures against power source voltage noise as explained above and is suppressed in power source voltage dependency of a delay time.